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MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR
PS12038 PS12038
FLAT-BASE TYPE FLAT-BASE TYPE INSULATED TYPE INSULATED TYPE
PS12038
INTEGRATED FUNCTIONS AND FEATURES
* 3 phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technology. * Inverter output current capability IO (Note 1): Type Name Motor Rating IO (100%) IO (150%; 60sec) PS12038 3.7 kW/400V AC 9.2Arms 13.8Arms (Note 1) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the above loading cases is defined as : IOP = IO x 2, TC < 100C
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
* P-Side IGBTs : Drive circuit, high-level-shift circuit, Bootstrap circuit supply scheme for single control-power-source drive, and Under voltage (UV) protection, * N-Side IGBTs : Drive circuit, DC-Link current sense and amplifier circuits for over-current protection, Control-supply under-voltage (UV) protection, and fault output (FO) signaling circuit. * Fault Output : N-side IGBT short circuit (SC), over-current (OC), and control supply under-voltage (UV). * Inverter Analog Current Sense : N-Side IGBT DC-Link Current Sense. * Input Interface : 5V CMOS/TTL compatible, Schmitt Trigger input, and Arm-Shoot-Through interlock protective function.
APPLICATION Acoustic noise-less 3.7kW/400V AC Class 3 phase inverters, motor control applications, and motors with built-in small size inverter package
PACKAGE OUTLINES
2.5 33.5
(24)
79 26
(21)
2.5 22
8-R1 Terminals Assignment : 4-R4 1. P 2. N 3. NC 4. U 5. V 6. W 7. FO 8. Vamp 9. GND 10. WN 11. VN 12. UN 13. WP 14. VP 15. UP 16. TH 17. VD 18. NC 19. CBW- 20. CBW+ 21. CBV- 22. CBV+ 23. CBU- 24. CBU+
0.5
24
3
(19) (18)
(7)
4-4
0.5 6.5
54
9 470.2 32 62 9.5
77
4-R2 1.4
3
81
12 7.62 7.62
1
(1)
(2)
(3)
(4) (5)
(6)
40.52 84 950.2 103
7.62 7.62 12
Detail : A 77 15
2
0~1.0
12.5
20.4
17
LABEL A
(Fig. 1)
9
3
2
Mar. 2002
MITSUBISHI SEMICONDUCTOR
PS12038
FLAT-BASE TYPE INSULATED TYPE
INTERNAL FUNCTIONS BLOCK DIAGRAM
UV Protection
Input signal conditioning (Interlock circuit)
P
VD UP VP WP UN VN WN FO V(amp)
Level shifter
Drive circuit
U V W
Fo Circuit
OC/SC Protection UV Protection Drive circuit
+-
TH
GND
N
(Fig. 2)
MAXIMUM RATINGS (Tj = 25C) INVERTER PART
Symbol Item VCC Supply voltage VCC(surge) Supply voltage (surge) VP or VN Each IGBT collector-emitter static voltage VP(S) or Each IGBT collector-emitter switching VN(S) voltage Ic(Icp) Each IGBT collector current Condition Applied between P-N Applied between P-N, Surge-value Applied between P-U.V.W, U.V.W-N Applied between P-U.V.W, U.V.W-N (Pulse) TC = 25C, "( )" means IC peak value Ratings 900 1000 1200 1200 25 (50) Unit V V V V A
CONTROL PART
Symbol VD, VDB VCIN VFO IFO Iamp Item Supply voltage Input signal voltage Fault output supply voltage Fault output current DC-Link IGBT current signal Amp output current Ratings -0.5 ~ 20 -0.5 ~ +7.5 -0.5 ~ +7.5 15 1 Unit V V V mA mA
Mar. 2002
MITSUBISHI SEMICONDUCTOR
PS12038
FLAT-BASE TYPE INSULATED TYPE
TOTAL SYSTEM
Symbol Tj Tstg TC VISO -- Item Junction temperature Storage temperature Module case operating temperature Isolation voltage Mounting torque Condition (Note 2) -- (Fig. 3) 60 Hz sinusoidal AC applied between all terminals and the base plate for 1 minute. Mounting screw: M3.5 Ratings -20 ~ +125 -40 ~ +125 -20 ~ +100 2500 0.78 ~ 1.27 Unit C C C Vrms N*m
(Note 2) : The indicated values are specified considering the safe operation of all the parts within the ASIPM. The max. ratings for the ASIPM power chips (IGBT & FWDi) is Tj < 150.
CASE TEMPERATURE MEASUREMENT POINT
LABEL
Tc
(Fig. 3)
THERMAL RESISTANCE
Symbol Rth(jc)Q Rth(jc)F Rth(cf) Item Junction to case Thermal Resistance Contact Thermal Resistance Inverter IGBT (1/6) Inverter FWDi (1/6) Case to fin, thermal grease applied (1 Module) Condition Min. -- -- -- Ratings Typ. -- -- -- Max. 1.5 2.0 0.045 Unit C/W C/W C/W
ELECTRICAL CHARACTERISTICS (Tj = 25C, VD = 15V, VDB = 15V unless otherwise noted)
Symbol VCE(sat) VEC ton tc(on) toff tc(off) Item Collector-emitter saturation voltage FWDi forward voltage Condition Tj = 25C, Input = ON, Ic = 5A, VD = VDB = 15V (Shunt voltage drop not included) Tj = 25C, -IC = 25A 1/2 Bridge inductive, Input = 5V 0V VCC = 600V, IC = 5A, Tj = 125C VD = 15V, VDB = 15V Note: ton, toff include delay time of the internal control circuit. Min. -- -- 0.3 -- -- -- Ratings Typ. -- -- 1.2 0.5 2.2 0.9 Max. 3.6 3.5 2.0 1.4 4.0 1.6 Unit V V s s s s
Switching times
trr FWDi reverse recovery time Short circuit endurance @VCC 800V, Input = 5V 0V (One-Shot) (Output, Arm, and Load, Short Circuit Modes) -20C Tj(start) 125C, 13.5V VD = VDB 16.5V Switching SOA @VCC 800V, Input = 5V 0V, Tj 150C IC < OC trip level, 13.5V VD = VDB 16.5V
-- 0.2 -- s * No destruction * FO output by protection operation * No destruction * No protecting operation * No FO output
Mar. 2002
MITSUBISHI SEMICONDUCTOR
PS12038
FLAT-BASE TYPE INSULATED TYPE
ELECTRICAL CHARACTERISTICS (Tj = 25C, VD = 15V, VDB = 15V unless otherwise noted)
Symbol ID IDB Vth(on) Vth(off) Ri fPWM tdead Item Circuit current Circuit current Input on threshold voltage Input off threshold voltage Input pull-up resistor PWM input frequency Arm shoot-through blocking time Condition Tj = 25C, VD = 15V, Vin = 5V Tj = 25C, VD = VDB = 15V, Vin = 5V Min. -- -- 0.8 2.5 -- -- 4.0 Ratings Typ. -- -- 1.4 3.0 50 10 -- Max. 50 5 2.0 4.0 -- 15 -- Unit mA mA V V k kHz s
-- 100 -- Input interlock sensing ns tint 2.5 2.0 1.5 V Vamp(100%) Inverter DC-Link IGBT current sense voltage 5.0 4.0 3.0 V Vamp(200%) output signal -- -- 5.0 V Vamp(250%) Inverter DC-Link IGBT current sense voltage 100 50 -- mV Vamp(0) output limit -- 46.5 39 Over current trip level A OC -- 10 -- Over current delay time s tOC -- 69.7 -- Short circuit trip level A SC -- 2 -- s tSC Short circuit delay time 12.75 12.0 11.0 V UVD VD UV trip level -20C ~ 100C 13.25 12.5 11.5 V UVDr VD UV reset level Supply circuit under VDB UV trip level 11.6 10.8 10.1 V UVDB voltage protection 12.1 11.3 10.6 V TC = Tj = 25C VDB UV reset level UVDBr -- 10 -- s UV delay time tdV -- 1.8 1.0 ms Fault output pulse width tFO Tj = 25C (Note 4) 1 -- -- A IFo(H) Open drain output (Note 4) Fault output current 15 -- -- mA IFo(L) 10.5 10 9.5 k Thermistor Resistance RTH Tc = 25C -- 3450 -- K Thermistor B constant B Resistance at 25C, 50C (Note 3) : The dead-time has to be set externally by the CPU; it is not part of the ASIPM internal functions. (Note 4) : Fault output signaling is given only when the internal OC, SC, & UV protection circuits are activated. The OC, SC and UV protection (and fault output) operate for the lower arms only. The OC and SC protection Fault output is given in a pulse format while that of UV protection is maintained throughout the duration of the under-voltage condition.
Applied between input terminal-Inside power supply TC 100C, Tj 125C Relates to corresponding inputs TC = -20C ~ +100C (Note 3) Relates to corresponding input (Fig. 6) IC = IOP(100%) VD = 15V IC = IOP(200%) Tj = 25C (Fig. 4) IC = IOP(250%) VD = 15V IC = 0A (Fig. 4) Tj = 25C (Fig. 5) Tj = 25C (Fig. 5) Tj = 25C (Fig. 5) Tj = 25C (Fig. 5)
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VD VDB VD, VDB VCIN(ON) VCIN(OFF) tdead TC fPWM tXX Item Supply voltage Supply voltage Supply voltage Supply voltage ripple Input on voltage Input off voltage Arm shoot-through blocking time Module case operating temperature PWM Input frequency Allowable input on-pulse width Condition Applied across P-N terminals Applied between VD-GND Applied between CBU+ & CBU-, CBV+ & CBV-, CBW+ & CBW- Applied between UP * VP * WP * UN * VN * WN and GND Relates to corresponding inputs TC 100C, Tj 125C Min. -- 13.5 13.5 -1 0 4.0 4.0 -- -- 1
Vamp
Ratings Typ. 600 15.0 15.0 -- -- -- -- -- -- --
Max. 800 16.5 16.5 +1 0.8 5.0 -- 100 15 --
Unit V V V V/s V V s C kHz s
INVERTER DC-LINK IGBT CURRENT ANALOGUE SIGNALING OUTPUT (TYPICAL)
5 VD = 15V Tj = 25C
4
Vamp (200%)
Vamp (V)
3
2 Vamp (100%) 1
0 0
(Fig. 4)
300 200 100 DC-LINK IGBT Current (%), (IC = IO 2)
Mar. 2002
MITSUBISHI SEMICONDUCTOR
PS12038
FLAT-BASE TYPE INSULATED TYPE
CURRENT ABNORMALITY PROTECTIVE FUNCTIONS
Ic(A) Short circuit trip level SC Over current trip level
Protection is achieved by monitoring and filtering the N-side DC-Bus current. When a current trip-level is exceeded all the N-side IGBTs are intercepted (turned OFF) and a fault-signal is output. After the fault-signal output duration (1.8msec (typ.)@25C), the interception is Reset at the following OFF input signal level (more than 4.0V).
OC
Collector current 0 2 10 tw (s)
(Fig. 5)
ARM-SHOOT-THROUGH INTER-LOCK PROTECTIVE FUNCTION
P-Side Input Signal : VCIN(p) ON N-Side Input Signal : VCIN(n) ON a3 P-Side IGBT Gate : VGE(p) 0 a2 b3 0 a1 a4 b1 b4
b2
N-Side IGBT Gate : VGE(n)
(Fig. 6) Description: (1) During the ON-State of either of the upper-arm or the lower-arm IGBT, the inter-lock protection circuit blocks any erroneous ON pulses (resulting from input noise) from triggering the other arm IGBT and thus it prevents the arm-shoot-through situation. (2) When two ON-signals are received for both the upper and the lower arms, the signal received first will be passed to the IGBT and the second signal will be blocked. The second signal will be passed to its corresponding IGBT immediately after the first signal is OFF. Note: This protective function provides no fault signaling output. The Dead-Time has to be set using the micro-controller (CPU). Operation: a1. P-side normal ON-signal P-side IGBT gate turns ON. a2. N-side erroneous ON-signal N-side IGBT gate remains OFF. a3. While P-side ON-signal remains P-side IGBT gate remains ON. a4. N-side normal ON-signal N-side IGBT gate turns ON. N-side normal ON-signal N-side IGBT gate turns ON. Simultaneous ON-signals P-side IGBT gate remains OFF. N-side receives OFF-signal N-side IGBT gate turns OFF. Immediately after (b3) P-side IGBT gate turns ON.
b1. b2. b3. b4.
RECOMMENDED I/O INTERFACE CIRCUIT
5V 5V 5.1k
ASIPM
VD(15V)
Up, Vp, Wp, Un, Vn, Wn CPU FO 10k Vamp 0.1nF GND
(Fig. 7) Mar. 2002

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